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Javad Tavakoli, Hossein Miri Lavasani and Samad Sheikhaei
A low-power and low-jitter 1.2 GHz Integer-N PLL (INPLL) is designed in a 65 nm standard CMOS process. A novel high-gain sampling phase detector (PD), which takes advantage of a transconductance (Gm) cell to boost the gain, is developed to increase the p...
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Shun Sang, Binhui Pei, Jiejie Huang, Lei Zhang and Xiaocen Xue
Voltage source (VS) control based on inertia synchronization is a novel phase lock loop (PLL)-less autonomous grid-synchronization control strategy suitable for the permanent magnet synchronous generator (PMSG)-based wind turbine. It can autonomously sen...
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Chenggang Yan, Chen Hu and Jianhui Wu
Automatic test equipment, Measurement instruments.
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Giuseppe Buja,Osley López
Pág. 314 a la 3
The paper starts by casting new light to the existing Phase Lock Loop (PLL) schemes used to synchronize the static converters with the grid under utility disturbances. Two approaches are pursued to detect the fundamental harmonic of the positive-sequence...
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