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Anastasios Fanariotis, Theofanis Orphanoudakis and Vassilis Fotopoulos
Having as a main objective the exploration of power efficiency of microcontrollers running machine learning models, this manuscript contrasts the performance of two types of state-of-the-art microcontrollers, namely ESP32 with an LX6 core and ESP32-S3 wi...
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Stavros Kalapothas, Manolis Galetakis, Georgios Flamis, Fotis Plessas and Paris Kitsos
In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and app...
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Sunkari Pradeep, Yogesh Kumar Sharma, Chaman Verma, Gutha Sreeram and Panugati Hanumantha Rao
Modern computers? network interface cards (NICs) are undergoing changes in order to handle greater data rates and assist with scaling problems caused by general-purpose CPU technology. The inclusion of programmable accelerators to the NIC?s data channel ...
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Ján Mach, Luká? Kohútka and Pavel Cicák
The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher...
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Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié
The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architectur...
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Kévin Mambu, Henri-Pierre Charles, Maha Kooli and Julie Dumas
In-memory computing (IMC) aims to solve the performance gap between CPU and memories introduced by the memory wall. However, it does not address the energy wall problem caused by data transfer over memory hierarchies. This paper proposes the data-localit...
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Jun Yuan, Qiang Zhao, Wei Wang, Xiangsheng Meng, Jun Li and Qin Li
As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an audio denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), a custom instructio...
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Pascal Pieper, Vladimir Herdt and Rolf Drechsler
RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes...
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Tiago Gomes, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong and Sandro Pinto
In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open R...
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Erez Manor, Avrech Ben-David and Shlomo Greenberg
The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware...
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