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Andrew Chamberlin, Andrew Gerber, Mason Palmer, Tim Goodale, Noel Daniel Gundi, Koushik Chakraborty and Sanghamitra Roy
Artificial Intelligence (AI) hardware accelerators have seen tremendous developments in recent years due to the rapid growth of AI in multiple fields. Many such accelerators comprise a Systolic Multiply?Accumulate Array (SMA) as its computational brain. ...
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Guillaume Devic, Gilles Sassatelli and Abdoulaye Gamatié
The execution of machine learning (ML) algorithms on resource-constrained embedded systems is very challenging in edge computing. To address this issue, ML accelerators are among the most efficient solutions. They are the result of aggressive architectur...
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Noel Daniel Gundi, Pramesh Pandey, Sanghamitra Roy and Koushik Chakraborty
Increasing processing requirements in the Artificial Intelligence (AI) realm has led to the emergence of domain-specific architectures for Deep Neural Network (DNN) applications. Tensor Processing Unit (TPU), a DNN accelerator by Google, has emerged as a...
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Tommaso Zanotti, Francesco Maria Puglisi and Paolo Pavan
Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides h...
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Mónica Y. Moreno-Revelo, Lorena Guachi-Guachi, Juan Bernardo Gómez-Mendoza, Javier Revelo-Fuelagán and Diego H. Peluffo-Ordóñez
Automatic crop identification and monitoring is a key element in enhancing food production processes as well as diminishing the related environmental impact. Although several efficient deep learning techniques have emerged in the field of multispectral i...
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Pavel Lyakhov, Maria Valueva, Georgii Valuev and Nikolai Nagornov
This paper proposes new digital filter architecture based on a modified multiply-accumulate (MAC) unit architecture called truncated MAC (TMAC), with the aim of increasing the performance of digital filtering. This paper provides a theoretical analysis o...
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Hwajeong Seo
In this paper, we present scalable multi-precision multiplication implementation and scalable multi-precision squaring implementation for 32-bit ARM Cortex-M4 microcontrollers. For efficient computation and scalable functionality, we present optimized Mu...
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