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Ali Asghar, Andreas Becher and Daniel Ziener
Exchanging FPGA-based implementations of cryptographic algorithms during run-time using netlist randomized versions has been introduced recently as a unique countermeasure against side channel attacks. Using partial reconfiguration, it is possible to shu...
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Hasan Irmak, Federico Corradi, Paul Detterer, Nikolaos Alachiotis and Daniel Ziener
This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Recon...
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Ziener, Ch.; Stobrawa, G.; Schwoerer, H.; Uschmann, I.; Sauerbrey, R.
Pág. 3313 - 3316
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