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ARTÍCULO
TITULO

A Novel Dimension-Reduction Technique for the Capacitance Extraction of 3-D VLSI Interconnects

Hong    
W    
Sun    
W-K    
Zhu    
Z-H    
Ji    
H    
Song    
B    
Dai    
W W-M    

Resumen

No disponible

PÁGINAS
pp. 1037 - 1044

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