Inicio  /  Applied Sciences  /  Vol: 10 Par: 14 (2020)  /  Artículo
ARTÍCULO
TITULO

Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

Kitae Lee    
Sihyun Kim    
Daewoong Kwon and Byung-Gook Park    

Resumen

Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations. Recently, wafer-level integrated tunneling-based ternary CMOS (TCMOS) has been successfully reported. However, the TCMOS requires large VDD (> 1 V), because a wide leakage region before on-current should be necessary to make the stable third voltage state. In this study, TCMOS consisting of ferroelectric-gate field effect transistors (FE-TCMOS) is proposed and its performance evaluated through 2-D technology computer-aided design (TCAD) simulations. As a result, it is revealed that the larger subthreshold swing and the steeper subthreshold swing are achievable by polarization switching in the ferroelectric layer, compared to conventional MOSFETs with high-k gate oxide, and thus the FE-TCMOS can have the more stable (larger static noise margin) ternary inverter operations at the lower VDD.

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