Resumen
This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power amplifier (PA). A detailed methodology for the evaluation of the active device?s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting in enhanced performance. A simplified model for the extraction of time-domain intrinsic voltage and current waveforms at the output of the main active core is introduced, enforcing the implementation process of the proposed quasi-inverse class F technique. The PA is fabricated in a 130 nm SiGe BiCMOS technology with fT/fmax=250/370 GHz" role="presentation">????/????????=250/370 GHzfT/fmax=250/370 GHz
f
T
/
f
m
a
x
=
250
/
370
GHz
and it is suitable for 5G applications. It achieves 33%" role="presentation">33%33%
33
%
peak power-added efficiency (PAE" role="presentation">??????PAE
P
A
E
), 18.8 dBm" role="presentation">18.8 dBm18.8 dBm
18.8
dBm
saturation output power Psat" role="presentation">????????Psat
P
s
a
t
, and 14.7 dB" role="presentation">14.7 dB14.7 dB
14.7
dB
maximum large-signal power gain G" role="presentation">??G
G
at the operating frequency of 38 GHz" role="presentation">38 GHz38 GHz
38
GHz
. The PA?s response is also tested under a modulated-signal excitation and simulation results are denoted in this paper. The chip size is 0.605×0.712 mm2" role="presentation">0.605×0.712 mm20.605×0.712 mm2
0.605
×
0.712
mm
2
including all pads.